Logic Design and Verification Engineer
Job Description
CA-Santa Clara, Tired of working on the same old boring stuff?. How about doing something new to change the world?.
How about working on an exciting next generation of computer memory architecture! – Job Description: – Logic design/synthesis/timing analysis or Logic Verification/Test Coverage – Responsible for design or verification, and presentation documents – Requirements: – MS EE/CS or BS EE/CS+2 years of exper [...]
Source ⇲
To apply, please visit the following URL:http://jobview.monster.com/Logic-Design-Verification-Engineer-Job-Santa-Clara-CA-US-216700991.aspx→
